1. Field of the Invention
The present invention relates to a semiconductor memory device, and more specifically, to a semiconductor memory device that is suitable for high-speed operation and capable of analyzing detailed failure.
2. Description of Related Art
A semiconductor memory device that includes SRAM cells is known. For example, FIG. 7 shows a semiconductor memory device where a precharge system used in a low power SRAM is mounted.
Such a low power system SRAM is also disclosed, for example, in FIG. 1 of Japanese Unexamined Patent Application Publication No. 2002-184198.
As shown in FIG. 7, a low power system SRAM 10 includes a memory array 11 formed of memory cells C00 and C01 arranged at intersections of bit line pairs (BP00, BP01) with a word line WORD, a precharge unit 12 that includes a plurality of precharge circuits PC00 and PC01 that precharge each bit line pair BP00 and BP01, and a Y-switch unit 13 that includes a plurality of Y-switch circuits YS00 and YS01 that select each bit line pair BP00 and BP01.
Each of the memory cells C00 and C01 is arranged at intersections of the bit line pairs BP00 and BP01 with the word line WORD, and is arranged in matrix as a whole.
In FIG. 7, two memory cells are shown as a representative example.
The memory cells C00 and C01 are well-known static memory cells (SRAMs). The precharge circuits PC00 and PC01 are arranged for each bit line pair BP00, BP01. Then, all the precharge circuits PC00 and PC01 are connected to a precharge control line LPC that is horizontally arranged, and collectively controlled by a block selection signal BLKsel that is supplied to the precharge control line LPC.
Further, FIG. 8 is a timing chart describing the operation of the low power system SRAM.
As the block selection signal BLKsel is changed from an L level to an H level in this low power system SRAM, the precharge operation of the precharge circuits PC00 and PC01 is turned off. Further, as the word line WORD becomes the H level and a Y switch selection signal Ysel00 becomes the H level to turn on the Y-switch circuit YS00 that selects the bit line pair BP00 to which the memory cell C00 which is the reading target is connected, data reading/writing is made possible from/to the memory cell C00.
In recent years, lines in a semiconductor memory device have been miniaturized in order to realize reduction in size, which may cause defects such as a short-circuit of the lines during a manufacturing process.
FIG. 9 shows an enlarged view of one of static memory cells (SRAMs).
For example, as shown in dashed lines in FIG. 9, such a defect may be caused that a node system of the SRAM shorts out with the GND. In order to overcome such a problem, it is required to analyze detailed failure of each memory cell regarding such a defect before mass production and to improve the product yield.
As one of the failure analyses of memory cells, one method is known that performs long write which is longer than normal writing on each memory cell C00 and C01.
In performing such a failure analysis, for the memory cell C00 which is the test target, the word line WORD is made to the H level, the Y-switch circuit YS00 is made to the ON state (Ysel is in the H level), and the potential difference corresponding to the write data is applied to the bit line pair BP00 for performing long write.
At this time, if current flows in the memory cell C00, there is a high possibility that any defect occurs that is connected to the GND side in a memory cell part node where High is written or any defect occurs that is connected to the VDD side in a memory cell part node where Low is written.
As such, by detecting the current that flows in the memory cell while executing the long write, the memory cell can be analyzed in detail.
In the related art, the above-described detailed test has been performed on the circuit of the SRAM memory as shown in FIG. 7 to improve the product yield.
Note that the failure test of the memory by the long write is also employed in a technique disclosed in Japanese Unexamined Patent Application Publication No. 2000-067598, for example, although its purpose is different from the one described above.
By the way, in recent years, high-speed operation has also been strongly desired along with the miniaturization of semiconductor memory devices.
However, the low power system SRAM as shown in FIG. 7 cannot cope with the high-speed operation.
According to the low power system SRAM shown in FIG. 7, in performing data reading/writing from/to the memory cell, the precharge circuits PC00 and PC01 are collectively turned off by the block selection signal BLKsel supplied to the precharge control line LPC.
Although only the memory cell C00 that is connected to the Y-switch circuit YS00 that is selected is read/written through a common bit line pair LIOT/LION, the potential at full amplitude is applied to the bit lines BT01 and BN01 even in the bit line pair BP01 which is not selected, as shown in FIG. 8.
Accordingly, all the bit line pairs BP00 and BP01 need to be charged to full capacity in order to execute the next precharge, which causes extremely large current consumption peak.
If there is a large current consumption peak, the power supply drop may easily be produced, which cannot assure the following high-speed operation or stable operation.
Accordingly, the low power system SRAM as shown in FIG. 7 is not suitable for the high-speed operation.
For example, a high-speed operation system SRAM as shown in FIG. 10 is known.
FIG. 10 is a circuit example in which a precharge system employed in a normal high-speed system SRAM or the like is mounted.
Such a high-speed system SRAM is disclosed also in FIG. 2, for example, of Japanese Unexamined Patent Application Publication No. 2002-313083.
In such a high-speed system SRAM, gates of the precharge circuits PC00 and PC01 are controlled in accordance with each of the Y-switch circuits YS00 and YS01.
FIG. 11 is a timing chart describing the operation of the high-speed system SRAM.
In such a high-speed system SRAM, the selection signal Ysel00 of the Y-switch circuit YS00 that selects the memory cell which is the reading/writing target and the word line WORD are controlled substantially in the same way.
When the selection signal YSW00 of the Y-switch circuit YS00 that selects the memory cell C00 which is the target of reading/writing is changed from the L level to the H level, the precharge circuit PC00 in accordance with the Y-switch circuit YS00 becomes the OFF state.
The data reading/writing from/to the memory cell C00 is made possible with this state.
When the precharge circuit is made OFF state and the data reading from the memory cell C00 is executed, for example, potentials of VDD, and GND are shown in the bit line pair BP00 (BT/BN00), respectively, which is connected to the memory cell C00 which is the writing/reading target.
On the other hand, the precharge circuit PC01 remains in the ON state in the bit line pair BP01 of the memory cell C01 which is not the target of reading/writing. Thus, the potential remains in the VDD with little change, or keeps VDD-a within a range of minor (a) fluctuation, if any.
Accordingly, for performing the precharge after the reading/writing operation, only the limited amount needs to be charged again, which causes only a small peak current due to the precharge.
Compared with FIG. 7 where the low power system SRAM collectively supplies charge to all the precharge circuits (PC00, PC01) for the precharge operation after the reading/writing operation, the high-speed system SRAM shown in FIG. 10 requires little current for the precharge and produces no abrupt current consumption peak, whereby the high-speed operation may be stably performed.